Given the following Omega network that allows 8 CPUs (P0 through P7) to
access 8 memory modules (M0 through M7):
(a) Show how the following connections through the network are achieved
(explain how each switch must be set).
(1) P0 -> M5
(2) P4 -> M2
(3) P7 -> M3
(b) Can these connections occur simultaneously or do they conflict?
Explain.
